Power MOSFETs (Metal-Oxide-Semiconductor Field Effect Transistors) are widely used and can be found in many electronic devices and apparatus. Well-known applications of power MOSFETs include, for example, power management and DC/DC conversion for desktop and notebook computers, portable devices and automotive electronics. Power MOSFETs are typically used as switching devices in such applications for controlling power delivery from the power source to the load. As a switching device, it is highly desirable to have minimal power loss across the device during power transfer. To achieve this, the on-resistance of a power MOSFET should be as low as possible. When translated into power MOSFET device design, a small cell pitch, that is, a small distance between adjacent cells, is highly desirable since a power MOSFET device typically comprises a plurality of transistor cells connected in parallel in order to meet with the large current requirements.
In the description below and throughout the specification, the terms “MOSFET” and “power MOSFET” are used interchangely to mean a power MOSFET to the extent appropriate and where the context permits. Planar VDMOS (Vertical Double-Diffused MOS) transistors are one of the most popular conventional power MOSFETs in which the channel is formed first by body implantation and then by lateral diffusion of dopants or impurities underneath the polycrystalline silicon (“polysilicon” or “poly” in short) gate at high temperature (around 1100° C. to 1150° C.) and with a long thermal cycle (around 90 to 300 minutes). Since the channel is formed by diffusion, the channel length needs to be long enough to have sustainable charges for a stable threshold voltage.
On the other hand, formation of a long channel length by lateral diffusion at high temperature and long thermal cycle means that the body-junction will have to be driven deeper and this will result in a deeper body-junction. A deeper body-junction consumes more lateral spacing between two adjacent body regions and also causes a more severe JFET (Junction Field Effect Transistor) effect. Aggravated JFET effect could induce early pinch-off in the area between the adjacent body-junctions and will degrade the device's on-state resistance. In addition, a power MOSFET with a deep body-junction also requires a thicker epitaxial (“epi”) layer in order to maintain the same blocking voltage. However, a thicker epi layer will result in a higher on-state resistance.
To alleviate undesirable JFET effect for a low on-resistance, an increase in cell size and a decrease in packing density seem inevitable. However, this translates into a higher chip cost. In addition, the typical square cell design of a planar VDMOS leads to a three-dimensional diffusion problem at the cell corners. This diffusion problem is primarily a result of a lower lateral diffusion rate of the impurity, which is typically about 20% lower than the vertical diffusion rate. Furthermore, as a result of t he known spreading effect at the cell corners, the diffusion rate of the impurities at the cell corners is even lower, at only around 50% of the lateral diffusion rate. This lower diffusion rate is even more severe for P-type impurities. Because of this lower diffusion rate, the channel length at the cell corners will become shorter and will lead to early punch-through breakdown of the channel at the square cell corners. As a result, the power MOSFET device may have a pre-mature breakdown due to shorter channel lengths at the cell corners.
Hence, it will be beneficial if there can be provided improved power MOSFETs and methods or processes for making same, which alleviate shortcomings of conventional MOSFETs or conventional methods of making same.